skip pulse in pwm & lower frequency PWM

[kyrophase]

Hello all,

i've been trying to setup a simple output from a 28x1 picaxe to give me 35 pulses and then skip one pulse and repeat (for varying pulse length from 33mS to 450uS) this timing is not suitable for the HPWM but neither is is suitable for pulse-out,wait as the measured time between commands i've found is 0.5mS to step a command and 1.25mS to do a 'repeat' or 'goto'.

I know that i ca up the clock frequency to 16Mhz but this still gives me a theoretical limit for time between commands and 'goto' of 125uS and 312.5uS. is there a methodology for a wider range of PWM frequencies, and a way of missing selected pulses from this output?

cheers for any comments

David

 

[hippy]

You could build external hardware as a modulo-36 counter then you only have to clock it at ther ight rate. You could use discrete logic, CPLD or even FPGA. Another ( non-PICAXE ) micro could be programmed just for this task.

 

[womai]

If you want to go the "external logic" route, I'd recommend the TMOD modules from Digilent (www.digilentinc.com). They are a 72 cell CPLD mounted on a standard 40 pin DIP carrier, so it's easy to breadboard them.

You could implement the circuit as a 72-state counter (a modulo-36 counter won't work bacause you need pulses, i.e. a high followed by a low, which doubles the necessary total count for one cycle) and feed out the LSB through logic that suppresses the last output.

To get the required wide frequency range (more than PWM may be able to do) I'd also implement a programmable clock divider that can be set from the Picaxe. The Picaxe can then drive the clock input using PWM or HWPWM, and change the division ratio as needed to get the low frequency range.

I have some TMODs lying in my drawer, so if you are interested I could give it a try and see if I can successfully implement this logic. Let me know.

Wolfgang

 

[kyrophase]

Hi,

Thank you for your offer Wolfgang, i'll probably just go with an alternative of someones pre-made solution (parrallel port based) for this part of my project.

The hardware you mention the C-MOD (i cant find t-mod) look interesting, what do you program them is? C++? i've been playing with the picaxes beacause i want to make a Engine control system simillar to the 'Megajolt jnr lite' which basically has a ADC and some logic and output a specific pulse length. but i want to add some enhancements and include datalogging via a uALFAT-TF module with temp monitoring etc.

i've gone with the picaxe because they are readilly available and easy to program. but am now a little concerned by the processing rates i can get it to achieve.

i'll probably have to use a pair of picaxes one with the data-logging stuff and one just for the engine control.

David

 

[MartinM57]

You'll never create a MJLJ-alike with a Picaxe - far, far too slow.....

 

[kyrophase]

any alternative sugestions for hardware?

 

[womai]

Yes, it's CMOD (the TMOD I confused it with is a project name from my "real" job

You program them using the free Xilinx ISE webpack, which accepts Verilog, VHDL (both are circuit-description language and have some significant learning curve), but also has a schematic editor - this is what I use so far, although learning VHDL is on my todo list. ISE converts the schematic into either Verilog or VHDL.

Programming a CPLD or FPGA is not super-hard, but definitely several steps above programming a Picaxe. Also, it's circuit design, as opposed to algorithmic programming on a Microcontroller, which makes for quite a different concept. On the upside, for things where it is a good fit it can be blazingly fast (100s of MHz) and parallel processing is a breeze. I knew some basic digital design before but it still took a few weeks to get comfortable with it.

Wolfgang

 

[womai]

Ok, couldn't hold myself - I implemented the basic circuitry on a Spartan FPGA (but would be trivial to re-target that to a CPLD, I don't use any FPGA-specific features). Good exercise for me anyway

Schematic see below. Simulation looks good, as well as function on the real hardware. To explain the circuit - it's a simple 8 bit counter, where I feed out the LSB (which toggles with each clock pulse). The CLK input would get hooked up the the Picaxe's PWM output (possibly with a selectable divider). The comparator in combination with the AND gate blocks out one pulse whenever the count reaches a certain value. The comparator also synchronously resets the counter to zero in this case. At the moment it compare against an 8 bit constant (value of 9 in the picture), but it would be trivial to route this out so you could set it (binary coded) through 8 jumpers or from the Picaxe. For trains of N pulses (and then one pause) you need to set the constant to 2*N+1, i.e. 73 in your actual case. The flip-flop at the output assures no glitches make it to the output.

Wolfgang

 

[Jaguarjoe]

any alternative sugestions for hardware?

This is a lot quicker and not too hard to program:

http://www.arduino.cc/

 

[womai]

Yes, but my design can run pulse lengths down to below 10ns and the Arduino can't

Just kidding; a good Microcontroller will do what is needed in this case and has less of a learning curve. I just liked the challenge, and FPGAs/CPLDs are wonderful if you need top speed for certain things, and/or extremely tight timing control. Also, once I had the design environment up and running it was actually easier than I thought to implement my first few simple designs. Now it's very much like the breadboarding that Stan likes so much, but without the messy pile of jumper wires on my desk, since it does virtually on the PC.

Wolfgang

 

[kyrophase]

Cheers for that wolfgang,

The CPLD implementation methodology looks realy nice, i much preffer visual programming (Labview style) to the code - its much easier to visualise and certainly more functional than just the standard function blocks.

I'll investigate the CMOD stuff, as it looks the way to go for the engine control unit and set the picaxe up as the data-logger and imobilliser unit (iButton).

in the end i'm wanting to create a engine control unit simillar to the MJLJ but with multiple engine maps for LPG and petrol and to enable multi-spark ignition for low revs. The timing logic should be easier to work out and the prospect of being able to parallel process would be a boon for data-logging.

Looking at the CMOD option there seem to be three variants, can anyone comment on them, the digilentic site does not offer as much information about their products as the rev-ed folks, and its all in acronyms which i'm not famillier with...

David

 

[womai]

I'd recommend the CMOD-95 which uses the XC9572XL device. First, it allows 5V logic interfacing (good for Picaxe), second it has 72 logic cells as opposed to 64 for the Coolrunner version. My design so far uses just 9 flip-flops, so you could fit a lot more into that device. (each CPLD logic cell consists of one flip-flop plus a sum-of-product logic fabric; many times the number of flip-flops is the limiting factor in a CPLD).

A hybrid approach - microcontroller for slower speed control & algorithmic functions, CPLD/FPGA for dedicated high-speed functions - is often a very good solution.

Let me know if you need any further help - I can certainly do some of the CPLD development for you, I like the challenge and can use the practice.

Wolfgang

 

[kyrophase]

Thanks for your offer,

i'll be getting the xilinx software downa and having a play, allong with sourcing some chips, wont go with the CMOD - postage to UK is prohibative and can get the parts locally to same effect.

will be a few weeks before i've got that up and running, also need to put the engine together first before i've time to realy get into the electrics side of things.

David