It would feature nothing but question marks for all output states, no matter what the logic states were of its three and a half inputs, but that would change if its clock didn't go either positive or negative, but only on the edge.
Of course, one could tie most of the inputs together as a following stage to invert the output for closed-collector applications.
It's a good gate to use when high propagation speed is paramount, or when one is working on a fuzzy illogic application, but not the best if one desires specific results.