Help with very Big EEPROM please

[MFB]

Having started on the development of a small and light data logger, that needs about ½ Mbyte of data storage, I narrowed the choice of memory options down to either a uDrive (www.4dsystems.com.au/prod.php?id=22) module or four 1024K byte EEPROMS (http://ww1.microchip.com/downloads/en/DeviceDoc/21941B.pdf).

The 24FC1025 looks like an elegant way to add large amounts of data storage to the PICAXE. Up to four of these chips can be placed on a single I2C bus. Speed should be quite respectable because this device has a 128-byte page buffer that can be written to EEPROM in 3mS. However, compared with a 64K EEPROM, address the 24FC1025 seems much more complex (a control byte needs to select block selects in addition to the normal chip selects).

Does anyone know if the PICAXE I2C bus is able to support this more complex format?

 

[Dippy]

This has been covered some time ago. Including example code.
Do a search on 24LC1025.

 

[womai]

From what I recall, addressing the 24FC1025 isn't that hard. For smaller EEPROMS, up to 24LC512, you send an I2C command to a specific slave address (set partially by the addres pin hookups on the EEPROM), with the first parameter being the location inside the chip you want to access. Since the location value is only 2 bytes, the largest you can access is 65 KBytes = 512 Kbits. For larger EEPROMS, the highest bits of the address are rolled into the slave address, so effectively it looks like two (or more) 512 kbit chips sitting on the I2C bus.

Wolfgang

 

[MFB]

Many thanks for the encouraging comments. Looks like the EEPROM route may be the best way to go (rather than SD cards). Unfortunately, my search did not find any example 24LC1025 interface code on the forum. I would therefore really appreciate any advice on the subject.

 

[GreenLeader]

I am working a logger project too.
My un-tested idea to get more storage from EEPROM's is to set up say 4 banks of 8x24LC256 chips. You can only have 8 unique addresses so there would be 4 chips sharing each of the 8 unique addresses.

The idea would be to write-protect the three banks you don't want to write to so that your i2c commands are only obeyed by one bank at a time. In principal you can have more than 4 banks - just limited by how many output lines you have to control the write protects.

Anyone see any problem with this approach?

The other thing that bothers me with EEPROM is the relatively small number of times you can write to it. I've read all the posts on this forum about this, but I'm still not totally clear..

Typically the guaranteed life is about 100,000 writes. So for a 24LC256, writing a byte at a time would take about 33,000 writes to fill the chip. So you could only fill the chip 3 times before it fails? By the time you get to the bigger chips, you can see you might only be able to write to them once before they die. Is it really this bad or am I missing some point?

Now I know the chances are you will get more than 1Million writes but that's still only filling the chip about 30 times - not really good enough for logging several channels at 5Hz or so.

I know that FRAM gets around the life problem but the price is about 10 times higher. Does anyone know if the FRAM chips are drop in replacements for 24LC256's, ie can you use existing hardware and code that already works for 24LC256's?

 

[womai]

Greenleader, that's a misunderstanding. The write life-time spec is the number of writes to a specific memory location, not the total number of writes to the chip. So a single 24LC512 chip can be written to e.g. loaction 0 exactly as often as two 25LC256 chips, and the total number of writes will be twice as high (assuming all memory locations are written to equally often).

There is no real advantage in using e.g. two 24LC512 chips as opposed to a single 24LC1025 chip. In fact, to a Picaxe the 1025 EEPROM will "look" exactly like two 512's with subsequent slave addresses. But of course the single 1025 uses less board space and is simpler to wire up than two 512s.

Wolfgang

 

[Dippy]

FRAM- I've only ever used the 24C64 FRAM and that was a simple swap. Obv the only code change was to get rid of the Pause Worked a treat.

Note: Unless you can find a dusty old shop, they are S/mount only. For breadboarding you'll need to make (or buy) an adaptor for SOIC-DIL/DIP.

Note2: (From experience). If you are making an adaptor make sure your DIP pins are less than 0.6mm diameter or else you can cause permanent damage to PCB ic-sockets if you use them.e.g. Harwin H3108-1 for pros, or bits of chopped off resistor legs.

 

[demonicpicaxeguy]

Typically the guaranteed life is about 100,000 writes. So for a 24LC256, writing a byte at a time would take about 33,000 writes to fill the chip. So you could only fill the chip 3 times before it fails? By the time you get to the bigger chips, you can see you might only be able to write to them once before they die. Is it really this bad or am I missing some point?

Now I know the chances are you will get more than 1Million writes but that's still only filling the chip about 30 times - not really good enough for logging several channels at 5Hz or so.

i have previously done some testing which proved that the 1millions write rating is possibly little charitable on microchips part

the test i did involved reading and writing to the same eeprom cell
it did fail but not until somthing like 5 odd million cycles and even then i dare say i could have pushed it even further if i had a properly regulated powersupply and some kind of tempreture control,

 

[hippy]

The idea would be to write-protect the three banks you don't want to write to so that your i2c commands are only obeyed by one bank at a time.

Sorry, I missed that earlier so a late reply ... No, that won't work. Write-protect will only stop data being written, all Eeproms on all banks will all still be active and respond to everything sent so you will run into problems.

You can however use the A2,A1,A0 address selects in a clever way to use these as chip selects for each bank. If you use A1, A0 as usual but take a 3-to-8 decoder, each output of that to a separate pair of Eeproms you can create an 8 bank x 4 Eeprom configuration, with the four you're interested in at addresses $A8, $AA, $AC, and $AE ( active-high o/p decoders ), $A0, $A2, $A4, $A6 ( active-low o/p )..

You could also use 2-to-4 decoder for 4 bank x 4 Eeprom, and if you used a pair of 2-to-4 decoders ( often available in a single package ) you can create a matrix of 4 x 4 x 2 Eeproms, only one of which will be at address $AC and another at $AE ( active-high o/p decoders ), $A0, $A2 ( active-low o/p ).

 

[MFB]

Faster write rate using page buffer?

Hippy, thanks for the ideas on addressing large amounts of EEPROM. Do you have any suggestions about how to use page buffering to increase write times? The 24LC1025 seems to take 3mS to write a single byte, or a full page buffer of data. If it is possible to employ the 24LC1025’s internal page buffer, using PICAXE I2C commands, then the data rate could be increased by x 128!

 

[Dippy]

If you write more than a byte in a single hit then it will be in page mode.
Check your addresses when doing this and don't write over a boundary. Easiest (with all these serial EEPROMs) to write in multiples that tot up to buffer size. Otherwise you can get funny results with overwrites.

 

[GreenLeader]

Sorry, I missed that earlier so a late reply ... No, that won't work. Write-protect will only stop data being written, all Eeproms on all banks will all still be active and respond to everything sent so you will run into problems.

Thanks Hippy, yes I overlooked how the EEPROMS would react to read commands

Thanks also for your other ideas - although they are somewhat over my head right now, they give me leads to look into for future development. Also, they stop me from wasting more time on my half-baked idea! So very sincere thanks