Circuit Diagram Query - 18X Datalogger

MikeM100

Member
Whilst helping a friend de-bug a programme I noticed what appears to be a discrepancy in the the circuit diagram of PICAXE-18X datalogger ?

(Datasheet (Version 1.2 26/08/06))

The Full Circuit diagram on Page 6 shows:

Out1 connected to SCL
Out4 connected to WP
Out5 connected to SDA

The Input/Output Pin Connections on Page 7 describes:

Output 1 - I2C SDA
Output 4 - I2C SCL
Output 5 - EEPROM Write Enable

The above connection list accurately reflects the PICAXE PinOut Descriptions in the datasheet - see below

Output 1 / I2C SDA data
Output 4 / I2C SCL Clock
Output 5

Is this actually an error in the circuit diagram or is the I2C for the logger application 'Bit Banged' ?

The circuit diagram appears throughout the Internet on various web sites but I notice that the VSM Logger App Circuit diagram differs from that in the datasheet and does (correctly ?)reflect the datasheet pin out descriptions .
 

hippy

Technical Support
Staff member
The datalogger uses the I2C hardware of the 18X so the connections on the board are -

Out 1, leg 7 - SDA
Out 4, leg 10 - SCL
Out 5, leg 11 - WP ( Write Protect )

The circuit diagram has the labelling of the 18X with SDA/SCL swapped over. I have made a note of that and will pass the information on.
 

westaust55

Moderator
MikeM100, firstly, welcome to the PICAXE forum.

The error you mention with the schematic diagram in the datasheet has been reported several time in the past as russbow has indicated.

Maybe Technical can arrange sooner than later to update this datasheet and prevent further occurances of this same question.
 

MikeM100

Member
Circuit Diagram Sorted

Thanks to all for 'sorting' my query. I did search the forum before posting but not obviously not well enough AND it was my first post !

I do find the PICAxe circuit diagrams a little strange and perhaps confusing for beginners. For example in the AXE110 full circuit, the pin out of the DS1307 & 24LCxx are industry standard 'top view' but the PICAxe itself is just a jumble of pin numbers.

I know this simplifies the drafting of the circuit diagram but in my opinion this is not helpful ? To further confuse the AXE110Datalogger.dsn file (VSM) shows a different (but correct) 'pin jumble' ?
 
Top