Another solution for Infrared Receiver of 32-bit Codes


Senior Member

This is a project that I completed back in 2008. It has been largely superseded by other solutions which use the more modern and much faster PICAXE chips. Having said that, the original model still serves its purpose of controlling my Home Theatre 'Receiver'.

I have posted this because a forum member asked how I used external hardware with a PICAXE to decode IR signals. I’m not expecting enthusiasts to rush off to build this solution to IR signal reception when modern PICAXEs can do it more elegantly.


Almost forgotten in 2021, the 08M was the forerunner of the 08M2. The 08M had just 256 bytes of program space, which doubled as EEPROM when required (and program space allowed). As well the 08M was limited to a top clock speed of 8MHz. My initial experiments showed that the 08M could not decode 32-bit IR signals without external help. Even with the external hardware, the 08M had to be dedicated to receiving and decoding the IR signals, then hand over the received code to another processor (PICAXE 40X) to utilise.

IR Signal Components

A CD4093 quad NOR gate with Schmitt Trigger inputs is used to separate the components of the IR signal. The IR receiver’s output is normally held low. When the receiver detects a 38kHz (or thereabouts) signal, its output goes low, returning to high soon after the signal disappears.

The three signals presented to the PICAXE are:
  • The rising edge or end of each carrier pulse is used as a clock signal to indicate to the PICAXE that a bit can be read.
  • One Schmitt trigger gate, configured as an integrator, detects the header pulse. The output of this gate goes high about 3.5mS after the leading edge of the header pulse. The diode causes the output to restore quickly after the pulse stops.
  • A second integrator is used to detect the longer ‘off’ periods of the ‘1’ bits. When data is present, the output of the second Schmitt trigger is pulled high by the presence of signal and stays high until the carrier is off for more than 1.5mS. This coincides with the longer ‘off’ periods of the ‘1’ bits. The third Schmitt trigger is configured as a monostable multivibrator. Its input is configured as a differentiator, triggered by the rising edge of the previous gate. This effectively creates a delayed pulse whenever a ‘1’ bit is received. By the time the PICAXE has responded to the clock signal, the output of this monostable will indicate the inverse of the received bit.

The PICAXE programme is critical to the operation of the IR receiver. The PICAXE must be run at 8MHz or higher in order to decode and store the IR data. The programme code structure is not very ‘pretty’ but has been optimized, firstly for speed and secondly to save programme space. This is necessary so that the smaller (now superseded) 08M or 14M chips can be used. The PICAXE chip must run faster than the incoming data so that overhead tasks, like saving data bytes and clearing the accumulator, can be completed before the next incoming bit needs to be read.

Due to the limited code space in the 08M, there is no overall time supervision that would cause a time-out if insufficient bits (clock pulses) are received. This may happen when a weak or reflected signal is received or possibly originating from some other remote control handpiece. The circuit and software will wait until a total of 34 rising edges are detected. Then the software will wait until a header pulse is detected, starting the decoding process again.

More modern M2-series PICAXE chips can run at 16 or 32MHz so the code could be structured differently.