Hi,
Presumably you mean the Serial Comms (USB interface) was disconnected (to avoid any risks of "Phantom Powering"); The PICaxe Serial Input pin (Leg 2)
must be tied to ground (via a resistor).
IMHO the best starting point is the
base PIC Data Sheet where most of these parameters are specified, not just "typical" but also "worst case" and at elevated temperature, etc., almost impossible to measure yourself and avoiding the risk of measuring an unfortuantely "good" or "bad" sample. So most of the influence of the Brownout Detector and oscillator speeds, and much more, can be determined directly from the manufactuer!
But a few words of warning: Read the "grey" (background) data which applies to the PICaxe chips, not the "white" data which applies to the (sometimes much lower current) LP or XLP "nanowatt" versions. Also beware that when an M2 PICaxe is "sleeping", the WDT oscillator is still running (to wake it up again).
The data sheet tells us that the "input leakage current" of an I/O pin is typically only 5
nanoAmps at up to 85 degrees C and the maximum is 200 nA, so difficult to measure and of little consequence (even over 18 pins of a 20M2). Note that this current includes not just the digital input (gate), but the ADC input (if available), the Output stage (in tri-state mode) and also any leakage through the electrostatic protection diodes! However, the /MR pin (aka the Input Only pin, Leg 3), appears to have rather higher leakage and "special attention" may be worthwhile here.
HOWEVER, that is not what the OP asked, nor can I find the required information in the Data Sheet! What is required is expained in the excellent Microchip "Hints 'n Tips" document as follows:
In CMOS logic there are
two (Complementary) input transistors connected in "Push-Pull" configuration across the supply rail. If the input voltage is close to zero volts, the "top" transistor actually conducts (to push the internal voltage High to Vdd, but the lower transistor is "off", so no current flows between the supply rail and ground. Similarly, if the input voltage is close to Vdd then the lower transistor conducts, but the upper transistor has no (Vgs) bias, so again no cuurent flows. However, if the input voltage is "somewhere in the middle" then potentially
both FETs are close to or above their threshold voltage, so there might be a through current from supply to ground!
In practice this doesn't seem to be a major problem and I often just leave any "spare" pins floating (even on chips with a large number of pins) with no obvious effects. But where power consumption may be a significant issue then it definitely is worth configuring unused pins as ADC inputs (if available and convenient) or with (internal) Weak Pullup resistors. But of course ensure that the pins really
are "floating" (i.e. with no external impedance at all to ground) or you may increase the supply drain by far more than you intened to save.
Cheers, Alan.