Timer1 module modified for 28X2

jaybeetoo

New Member
This module enables you to time events in milliseconds using Timer1. It is the module written by Jeremy Leach but I've amended it to work on the 28X2.

Code:
#PICAXE 28X2

#rem
#
#######################################################
# TIMER1 test code						#
#######################################################
#endrem


; Timer1 result
	symbol Timer1ValueW	= W1
	symbol Timer1ValueL	= b2
	symbol Timer1ValueH	= b3

; Variables for test
	symbol TimePeriod	= W2

Initialise:
	SetFreq M8
	gosub InitialiseTimer1
	
Main:
	for TimePeriod = 0 to 520 step 10	; in milliseconds
				
		; Reset Timer1
		gosub ResetAndStartTimer1
		
		; Simulate a delay due to a block of code executing...
		pause TimePeriod
		
		; Get the elapsed time
		gosub GetTime
	
		; Transmit the results
		sertxd (CR,LF, "Paused = ", #TimePeriod, "ms. Measured = ", #Timer1ValueW, "ms.")
	
	next TimePeriod
 
 	goto main

	end

#rem
#
#######################################################
# TIMER1 'MODULE'. J.Leach December 2006			#
#	Modified for 28X2 by jaybeetoo May 2013		#
#######################################################

This module enables you to time events in milliseconds using Timer1. 

At 8MHz clock the maximum time that can be meaured is 524ms

These routines have been written following discovery of the detail 
by the Happy Hippy.

#endrem

; Registers
	symbol SFR_T1CON	= $CD	; TIMER1 CONTROL REGISTER
	symbol SFR_TMR1H	= $CF	; Timer1 high byte
	symbol SFR_TMR1L	= $CE	; Timer1 low byte
	symbol SFR_PIR1	= $9E	; PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

; TXCON: TIMER1 CONTROL REGISTER
;	bit 7-6 TMRxCS<1:0>: Timer1/3/5 Clock Source Select bits
;			11 =Reserved. Do not use.
;			10 =Timer1/3/5 clock source is pin or oscillator:
;				If TxSOSCEN = 0:
;					External clock from TxCKI pin (on the rising edge)
;				If TxSOSCEN = 1:
;					Crystal oscillator on SOSCI/SOSCO pins
;			01 =Timer1/3/5 clock source is system clock (FOSC)
;			00 =Timer1/3/5 clock source is instruction clock (FOSC/4)
;	bit 5-4 TxCKPS<1:0>: Timer1/3/5 Input Clock Prescale Select bits
;			11 = 1:8 Prescale value
;			10 = 1:4 Prescale value
;			01 = 1:2 Prescale value
;			00 = 1:1 Prescale value
;	bit 3 TxSOSCEN: Secondary Oscillator Enable Control bit
;			1 = Dedicated Secondary oscillator circuit enabled
;			0 = Dedicated Secondary oscillator circuit disabled
;	bit 2 TxSYNC: Timer1/3/5 External Clock Input Synchronization Control bit
;			TMRxCS<1:0> = 1X
;			1 = Do not synchronize external clock input
;			0 = Synchronize external clock input with system clock (FOSC)
;
;			TMRxCS<1:0> = 0X
;			This bit is ignored. Timer1/3/5 uses the internal clock when TMRxCS<1:0> = 1X.
;	bit 1 TxRD16: 16-Bit Read/Write Mode Enable bit
;			1 = Enables register read/write of Timer1/3/5 in one 16-bit operation
;			0 = Enables register read/write of Timer1/3/5 in two 8-bit operation
;	bit 0 TMRxON: Timer1/3/5 On bit
;			1 = Enables Timer1/3/5
;			0 = Stops Timer1/3/5
;				Clears Timer1/3/5 Gate flip-flop
	symbol T1CON	= b0
	symbol TMR1CS1	= bit7
	symbol TMR1CS2	= bit6
	symbol T1CKPS1	= bit5
	symbol T1CKPS0	= bit4
	symbol T1SOSCEN	= bit3
	symbol T1SYNC	= bit2
	symbol T1RD16	= bit1
	symbol TMR1ON	= bit0

; PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
;	bit 7 Unimplemented: Read as &#8216;0&#8217;.
;	bit 6 ADIF: A/D Converter Interrupt Flag bit
;		1 = An A/D conversion completed (must be cleared by software)
;		0 = The A/D conversion is not complete or has not been started
;	bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit
;		1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read)
;		0 = The EUSART1 receive buffer is empty
;	bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit
;		1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)
;		0 = The EUSART1 transmit buffer is full
;	bit 3 SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit
;		1 = The transmission/reception is complete (must be cleared by software)
;		0 = Waiting to transmit/receive
;	bit 2 CCP1IF: CCP1 Interrupt Flag bit
;		Capture mode:
;		1 = A TMR1 register capture occurred (must be cleared by software)
;		0 = No TMR1 register capture occurred
;		Compare mode:
;		1 = A TMR1 register compare match occurred (must be cleared by software)
;		0 = No TMR1 register compare match occurred
;		PWM mode:
;		Unused in this mode
;	bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
;		1 = TMR2 to PR2 match occurred (must be cleared by software)
;		0 = No TMR2 to PR2 match occurred
;	bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
;		1 = TMR1 register overflowed (must be cleared by software)
;		0 = TMR1 register did not overflow
	symbol PIR1		= b0
	symbol TMR1IF	= bit0

InitialiseTimer1:
	; Sets the TIMER1 control register
	TMR1CS1	= 0	; Timer1 clock source is instruction clock (FOSC/4)
	TMR1CS2	= 0	; Timer1/3/5 clock source is instruction clock (FOSC/4)
	T1CKPS1	= 1	; 1:8 Prescale value
	T1CKPS0	= 1	; 1:8 Prescale value
	T1SOSCEN	= 0	; Dedicated Secondary oscillator circuit disabled
	T1SYNC	= 1	; Do not synchronize external clock input
	T1RD16	= 0 	; Enables register read/write of Timer1 in two 8-bit operation
	TMR1ON	= 0	; Stops Timer1

	pokeSFR SFR_T1CON, T1CON	; Set TIMER1 control register

	return

ResetAndStartTimer1:
	; Clear Timer1 and the interrupt (overflow) flag, Start Timer1
	
	; Set Timer1 to 0
	pokeSFR SFR_TMR1H, 0
	pokeSFR SFR_TMR1L, 0
	
	; Clear Timer 1 overflow interrupt
	peekSFR SFR_PIR1, PIR1
	TMR1IF = 0
	pokeSFR SFR_PIR1, PIR1
	
	; Start Timer1
	peekSFR SFR_T1CON, T1CON
	TMR1ON   = 1	;	 Enables Timer1
	pokeSFR SFR_T1CON, T1CON

	return

GetTime:
	; Stop Timer1, load the results into Timer1ValueW and convert it
	; to milliseconds (assumes 8MHz clock)
	
	; Stopt Timer1
	peekSFR SFR_T1CON, T1CON
	TMR1ON   = 0	;	 Stops Timer1
	pokeSFR SFR_T1CON, T1CON
	
	; Get result
	peekSFR SFR_TMR1H, Timer1ValueH
	peekSFR SFR_TMR1L, Timer1ValueL
	
	; Convert result to milliseconds
	Timer1ValueW = Timer1ValueW / 250
	
	; Check for an overflow
	peekSFR SFR_PIR1, PIR1
	if TMR1IF = 1 then
		 Timer1ValueW = Timer1ValueW + 262
	endif
	
	return
This is the output:

Paused = 50ms. Measured = 51ms.
Paused = 60ms. Measured = 61ms.
Paused = 70ms. Measured = 71ms.
Paused = 80ms. Measured = 81ms.
Paused = 90ms. Measured = 91ms.
Paused = 100ms. Measured = 101ms.
Paused = 110ms. Measured = 111ms.
Paused = 120ms. Measured = 121ms.
Paused = 130ms. Measured = 131ms.
Paused = 140ms. Measured = 141ms.
Paused = 150ms. Measured = 151ms.
Paused = 160ms. Measured = 161ms.
Paused = 170ms. Measured = 171ms.
Paused = 180ms. Measured = 181ms.
Paused = 190ms. Measured = 191ms.
Paused = 200ms. Measured = 201ms.
Paused = 210ms. Measured = 211ms.
Paused = 220ms. Measured = 220ms.
Paused = 230ms. Measured = 230ms.
Paused = 240ms. Measured = 240ms.
Paused = 250ms. Measured = 250ms.
Paused = 260ms. Measured = 260ms.
Paused = 270ms. Measured = 270ms.
Paused = 280ms. Measured = 280ms.
Paused = 290ms. Measured = 290ms.
Paused = 300ms. Measured = 300ms.
Paused = 310ms. Measured = 310ms.
Paused = 320ms. Measured = 320ms.
Paused = 330ms. Measured = 330ms.
Paused = 340ms. Measured = 340ms.
Paused = 350ms. Measured = 350ms.
Paused = 360ms. Measured = 360ms.
Paused = 370ms. Measured = 370ms.
Paused = 380ms. Measured = 380ms.
Paused = 390ms. Measured = 389ms.
Paused = 400ms. Measured = 399ms.
Paused = 410ms. Measured = 409ms.
Paused = 420ms. Measured = 419ms.
Paused = 430ms. Measured = 429ms.
Paused = 440ms. Measured = 439ms.
Paused = 450ms. Measured = 449ms.
Paused = 460ms. Measured = 459ms.
Paused = 470ms. Measured = 469ms.
Paused = 480ms. Measured = 479ms.
Paused = 490ms. Measured = 489ms.
Paused = 500ms. Measured = 499ms.
Paused = 510ms. Measured = 509ms.
Paused = 520ms. Measured = 519ms.
 
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