As per the previous thread (<A href='http://www.rev-ed.co.uk/picaxe/forum/topic.asp?topic_id=4381&forum_id=24&Topic_Title=SRAM+Controller&forum_title=PICAXE+Forum&M=False&S=True' Target=_Blank>External Web Link</a>), I have done some more work on this project, albeit very slowly. I promised an update, so here it is:
I finally got the SRAM and PIC interfacing properly and have successully managed to access 256 bytes of the RAM, of the 32Kbytes.
Using unoptimised code (lots of redundancy so that I was sure that stuff worked correctly - eg. setting pins states one by one, not in blocks) and running at 4MHz, it can write 256 bytes to 256 locations (65536 bytes in total) in around 30 seconds - roughly <b>2K bytes per second </b> . Without all the serial debugging code I have which indicates that the controller is "writing", "verifying" and "verified" the data, the throughput should be substantially higher.
Although the data was written in sequential addresses (location 0, the location 1, ...), the address was set manually for each read/write process which means that random read/write times should be exactly the same.
Hopefully, I will be able to expand the current system with another shift register to access all 32K bytes of the data. In the near future (don't have time to do this part for another 2 months or so) I hope to construct a PCB for this project and use it with a PICAXE chip (or other controller). I also hope to add a 1F supercap to the PCB to allow the SRAM to act more like an NVRAM module.
More to come... (as time permits)
<b><i>ylp88 </b> </i>
I finally got the SRAM and PIC interfacing properly and have successully managed to access 256 bytes of the RAM, of the 32Kbytes.
Using unoptimised code (lots of redundancy so that I was sure that stuff worked correctly - eg. setting pins states one by one, not in blocks) and running at 4MHz, it can write 256 bytes to 256 locations (65536 bytes in total) in around 30 seconds - roughly <b>2K bytes per second </b> . Without all the serial debugging code I have which indicates that the controller is "writing", "verifying" and "verified" the data, the throughput should be substantially higher.
Although the data was written in sequential addresses (location 0, the location 1, ...), the address was set manually for each read/write process which means that random read/write times should be exactly the same.
Hopefully, I will be able to expand the current system with another shift register to access all 32K bytes of the data. In the near future (don't have time to do this part for another 2 months or so) I hope to construct a PCB for this project and use it with a PICAXE chip (or other controller). I also hope to add a 1F supercap to the PCB to allow the SRAM to act more like an NVRAM module.
More to come... (as time permits)
<b><i>ylp88 </b> </i>