Hello.
Some of you may remember my earlier posts as regards a signalling interlocking project and requiring extra inputs.
You will be glad to know I have now got onto a more level part of the learning curve and have started to write the code. The problem now is I have used 3823 bytes of memory and have only done threequarters of the code.
I am enclosing the code for one signal lever to see if it can be made more efficient. As it is, the code works and does everything it should. All the inputs should really be and`ed together, but a bit/set cannot be used after an and.
Every statement must be true for the lever to be released, but any one false statement must lock the lever.
I am using a 40X2 with six 23017 expanders. All the pins on the 40X2 are in use as ouputs to the lever frame and five expanders are used as inputs and one as outputs.
If the code cannot be made much more efficient, then can I add an extra Picaxe to share the load for the final signal levers?
I have had to cut the code by several lines as it was too long to post.
Some of you may remember my earlier posts as regards a signalling interlocking project and requiring extra inputs.
You will be glad to know I have now got onto a more level part of the learning curve and have started to write the code. The problem now is I have used 3823 bytes of memory and have only done threequarters of the code.
I am enclosing the code for one signal lever to see if it can be made more efficient. As it is, the code works and does everything it should. All the inputs should really be and`ed together, but a bit/set cannot be used after an and.
Every statement must be true for the lever to be released, but any one false statement must lock the lever.
I am using a 40X2 with six 23017 expanders. All the pins on the 40X2 are in use as ouputs to the lever frame and five expanders are used as inputs and one as outputs.
If the code cannot be made much more efficient, then can I add an extra Picaxe to share the load for the final signal levers?
I have had to cut the code by several lines as it was too long to post.
Code:
[color=Green];*********************************************************************************************88*************
; Signal 19 locking
;************************************************************************************************************[/color]
[color=Blue]if [/color][color=Purple]b10 [/color][color=DarkCyan]bit [/color][color=Navy]4 [/color][color=DarkCyan]clear [/color][color=Blue]then [/color][color=Green]; points 29 reversed
[/color][color=Blue]if [/color][color=Purple]b10 [/color][color=DarkCyan]bit [/color][color=Navy]3 [/color][color=DarkCyan]clear [/color][color=Blue]then [/color][color=Green]; points 28 reversed
[/color][color=Blue]low C.6 [/color][color=Green]; signal 19 free
[/color][color=Blue]if [/color][color=Purple]b10 [/color][color=DarkCyan]bit [/color][color=Navy]7 [/color][color=DarkCyan]clear [/color][color=Blue]then [/color][color=Green]; points 32 reversed
[/color][color=Blue]low C.6
if [/color][color=Purple]b6 [/color][color=DarkCyan]bit [/color][color=Navy]5 [/color][color=DarkCyan]clear [/color][color=Blue]then [/color][color=Green]; points 34 normal
[/color][color=Blue]low C.6
if [/color][color=Purple]b11 [/color][color=DarkCyan]bit [/color][color=Navy]4 [/color][color=DarkCyan]set [/color][color=Blue]then [/color][color=Green]; TC J2 clear
[/color][color=Blue]low C.6
if [/color][color=Purple]b4 [/color][color=DarkCyan]bit [/color][color=Navy]0 [/color][color=DarkCyan]set [/color][color=Blue]then [/color][color=Green]; TC C6 clear
[/color][color=Blue]low C.6
if [/color][color=Purple]b5 [/color][color=DarkCyan]bit [/color][color=Navy]0 [/color][color=DarkCyan]set [/color][color=Blue]then [/color][color=Green]; TC B4 clear
[/color][color=Blue]low C.6
if [/color][color=Purple]b5 [/color][color=DarkCyan]bit [/color][color=Navy]1 [/color][color=DarkCyan]set [/color][color=Blue]then [/color][color=Green]; TC B3 clear
[/color][color=Blue]low C.6
if [/color][color=Purple]b5 [/color][color=DarkCyan]bit [/color][color=Navy]2 [/color][color=DarkCyan]set [/color][color=Blue]then [/color][color=Green]; TC B" clear
[/color][color=Blue]low C.6
if [/color][color=Purple]b3 [/color][color=DarkCyan]bit [/color][color=Navy]2 [/color][color=DarkCyan]set [/color][color=Blue]then [/color][color=Green]; signal 38 on
[/color][color=Blue]low C.6
if [/color][color=Purple]b2 [/color][color=DarkCyan]bit [/color][color=Navy]1 [/color][color=DarkCyan]set [/color][color=Blue]then [/color][color=Green]; signal 46 on
[/color][color=Blue]low C.6 [/color][color=Green]; signal 19 free
[/color][color=Blue]else high C.6 [/color][color=Green]; signal 19 locked
[/color][color=Blue]endif
else high C.6
endif
else high C.6
endif
else high C.6
endif
else high C.6
endif
else high C.6
endif
else high C.6
endif
else high C.6
endif
else high C.6
endif
else high C.6 [/color][color=Green]; signal 19 locked[/color]
[color=Blue]endif
endif
HI2COUT [PLAIN][[/PLAIN]mcp23017f[PLAIN]][/PLAIN][/color][color=Black], [/color][color=Blue]OLATA[/color][color=Black], [/color][color=Blue]([/color][color=Purple]b10[/color][color=Blue])
HI2COUT [PLAIN][[/PLAIN]mcp23017e[PLAIN]][/PLAIN][/color][color=Black], [/color][color=Blue]OLATB[/color][color=Black], [/color][color=Blue]([/color][color=Purple]b9[/color][color=Blue])[/color]