Picaxe 18M2+ Available Memory

pmolsen

Senior Member
Is there any manual that gives a comprehensive description of the memory in the 18M2+ please? I want to know how much of each there is, what overlaps what, plus the life expectancy (write cycles) of each type.

Manual 1 page 52 describes the different types of memory, but it says for example that Table memory only applies to the X1 and X2 parts whereas in Manual 2 under Table it says it applies to 18M2

Where it describes Table memory it seems to imply that it is deducted from available program memory but that is not clearly spelled out, the way the use of EEPROM data is described for the M parts.

EEPROM data is supposedly not deducted from program memory for 18M2+ but that is not well explained.

I think there are the following different types and amounts of memory at present on the 18M2+ (excluding Special Function variables):

- Program flash memory (2048 bytes) 100k rewrites?
- Data memory (EEPROM memory) (512 bytes) ?? rewrites
- Memory accessed via Table (512 bytes) ?? rewrites
- General Purpose variables b0-b27 ?? rewrites
- Storage Variables (peek/poke) (512 bytes) ?? rewrites
 
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Technical

Technical Support
Staff member
As WA55 states, the comparison table in the back of the manual in the M2 parts appendix (duplicated in the m2 product briefing) has most of this info.
Table is a separate different part of program memory, so although it uses program memory technology it does not actually decrease the 2048 byte memory limit.
EEPROM uses data memory, not program memory, and is 256 bytes on all M2/X2 parts.
 

pmolsen

Senior Member
Thanks for that. So just to confirm, EEPROM memory does not reduce the program memory, as it does on the M2 parts?

That just leaves the number of rewrite cycles each can bear to be outlined. What I mainly want to know for is to decide what the impact is of changing my program to use Table instead of EEPROM, given that it has twice as much.

I should also have asked when Table memory is cleared. On program download? On power off?
 

pmolsen

Senior Member
Thanks for that.
When is Table memory cleared please?

Another question. Maybe I should ask in a separate topic. Given that one can buy a 64Gb micro-SD card, which is tiny, why is it that these Microchip devices seem to struggle to provide a billionth of that memory capacity?
 

Buzby

Senior Member
.. Given that one can buy a 64Gb micro-SD card, which is tiny, why is it that these Microchip devices seem to struggle to provide a billionth of that memory capacity?
Because a tiny little MCU doesn't usually need 64Gb.

If there was a huge market for a tiny processor with 64Gb of flash built in then I'm sure Microchip, or somebody else, would provide it.
 

nick12ab

Senior Member
Thanks for that.
When is Table memory cleared please?
When you perform a download without using the #no_table directive.


Another question. Maybe I should ask in a separate topic. Given that one can buy a 64Gb micro-SD card, which is tiny, why is it that these Microchip devices seem to struggle to provide a billionth of that memory capacity?
64Gb = 8GB. PICAXEs have a lot more than 8 bytes of program memory, and also your 64 giga-bit memory card will use flash memory which is cheaper than sstandard EEPROM but requires that it is erased in large blocks just to change one byte rather than a byte at a time like EEPROM and the 8-bit microcontrollers aren't (currently) powerful enough for this. Also, a PICAXE costs considerably less than a 8GB memory card (unless bought from a dodgy ebay seller).

However PICAXE has made a lot of advancements recently with the M2 parts, X2 parts and "X2.5" parts too. I wonder when the X3, M3 and X4 parts will come out.

In a few years time, it's possible that there will be PICAXEs with multi-GB program memory and clock speeds in GHz...

 

Technical

Technical Support
Staff member
Thanks for that.
When is Table memory cleared please?
Nick is correct for X2 parts, but not for M2 parts, as #no_table is implied by default on M2 parts.

So around the other way, table memory is only programmed on M2 parts when you add a 'table' command.
It doesn't actually need to be cleared, as it is 'read only' anyway. Therefore if you are going to use it you really need to use a table command to start with!
If you want it cleared for some reason just add table 0,(0)

Cost of chip = size of silicon wafer. Bigger memory = bigger wafer = more cost. Remember a micro wafer is many times more complex than the simple memory wafer found in memory cards.
 

tiscando

Senior Member
In a few years time, it's possible that there will be PICAXEs with multi-GB program memory and clock speeds in GHz...
That would be similar to putting DOS onto a(n old) PC (perhaps with yesteryear's 2.6GHz celeron like mine), and using a BASIC program editor to make DOS programs that use the parallel port as GPIO (like PICAXE pins!).

I have a PICAXE-25KVMDX86, where the 25 means the 25 IO pins on 1 serial port and 1 parallel port combined, KVM means it has keyboard input, video output and mouse input, D means it has a 10GB hard drive, and X86 means it's an 8086-compatible processor connected to 768MB of RAM. It can be self-programmed through its keyboard & video interface in any language available, although me being advanced and wanting to probe the hardware registers, I use Assembler code the most. It also has a large set of pre-programmed subroutines, both DOS and BIOS, for displaying text on the video output etc. The snag is that its power consumption is about 300W, and it uses floppy disks instead of EEPROM chips. It's not a PICAXE - it is an IBM PC-compatible box made in 2003, used as a powerful microcontroller (without modifying the motherboard - so not really a microcontroller). And I didn't mention the PCI and IDE buses - it can easily be converted to a PICAXE-42KVMDX86 by adding a second parallel port, or to a PICAXE-25KVMFX86 by replacing the hard drive with a compact flash card.
 
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pmolsen

Senior Member
When I looked at the #no_table directive it said that it only applied to X1 and X2 parts.

In relation to the total memory size, I don't want 64GB (what I first meant, not 64Gb), which is already available in a micro SD card. I just struggle to understand why Microchip can't even provide one billionth of that (as I first said) in RAM variables (ie. 64 bytes instead of 28 bytes), or one millionth of that in program storage.
 

nick12ab

Senior Member
That would be similar to putting DOS onto a(n old) PC (perhaps with yesteryear's 2.6GHz celeron like mine), and using a BASIC program editor to make DOS programs that use the parallel port as GPIO (like PICAXE pins!).

I have a PICAXE-25KVMDX86, where the 25 means the 25 IO pins on 1 serial port and 1 parallel port combined, KVM means it has keyboard input, video output and mouse input, D means it has a 10GB hard drive, and X86 means it's an 8086-compatible processor connected to 768MB of RAM. It can be self-programmed through its keyboard & video interface in any language available, although me being advanced and wanting to probe the hardware registers, I use Assembler code the most. It also has a large set of pre-programmed subroutines, both DOS and BIOS, for displaying text on the video output etc. The snag is that its power consumption is about 300W, and it uses floppy disks instead of EEPROM chips. It's not a PICAXE - it is an IBM PC-compatible box made in 2003, used as a powerful microcontroller (without modifying the motherboard - so not really a microcontroller). And I didn't mention the PCI and IDE buses - it can easily be converted to a PICAXE-42KVMDX86 by adding a second parallel port, or to a PICAXE-25KVMFX86 by replacing the hard drive with a compact flash card.
Don't forget that newer PICAXEs can execute code from i2c EEPROMs now which offers some extra expansion.

Back to the off-topic computing-related PICAXE topic, the PICAXE-479 is a "photoshopped*" 1.2GHz Celeron-M featuring 32-bit processing, floating point mathematics (hint) and 512KB of integrated RAM!



Here's some more processors that could be photoshopped to become PICAXEs:

700MHz Celeron with 128KB cache - PICAXE-370X22


266MHz Pentium II-M with 512KB cache - PICAXE-280X21


The Netburst-based Celerons (or PowerPC processors) should be turned into Genie chips.


*Edited in a trial version of CorelDRAW X5

In relation to the total memory size, I don't want 64GB (what I first meant, not 64Gb), which is already available in a micro SD card. I just struggle to understand why Microchip can't even provide one billionth of that (as I first said) in RAM variables (ie. 64 bytes instead of 28 bytes), or one millionth of that in program storage.
It's not 28 bytes of RAM, its 256 or usually more, it's just that only 28 or 56 are available via named variables. Even computers rarely have 64GB of RAM. Also, this RAM is probably a billion times faster than your 2MB/s microSD card.

ADDED: SSD vs HDD vs 64 gigabit microSD card
Well the microSD card did better than the 1GB SD card (not shown)

[HR][/HR]
This thread will probably just turn into images of benchmark results for SD cards and who has the photoshopped PICAXE with the most pins.
 
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Technical

Technical Support
Staff member
in RAM variables (ie. 64 bytes instead of 28 bytes),
There are actually 1024 on the 18M2+ silicon. 512 are reserved for use by the PICAXE firmware, the other 512 are available to the end user by @bptr, peek and poke (and can be preloaded via tablecopy).

Microchip could add as many as they like, it just comes down to cost, more RAM = more silicon = more expensive chip. And most micro projects don't need lots of RAM.
 

pmolsen

Senior Member
I looked at the Microchip datasheets but could find no mention of Table storage at all, let alone how many write cycles it is good for. I am therefore still no closer to finding out whether there would be any down side to converting my current program to use Table memory instead of EEPROM (read/write) memory for storing static data, thereby doubling the capacity. (The data only changes about once every 4 years).

I could combine the two storage types but I would prefer not to complicate the program, which is already at the storage size limit.
 

Technical

Technical Support
Staff member
I looked at the Microchip datasheets but could find no mention of Table storage at all, let alone how many write cycles it is good for. I am therefore still no closer to finding out whether there would be any down side to converting my current program to use Table memory instead of EEPROM (read/write) memory for storing static data, thereby doubling the capacity. (The data only changes about once every 4 years).

I could combine the two storage types but I would prefer not to complicate the program, which is already at the storage size limit.
You are still misunderstanding, table is part of program memory, there is no separate 'style' of table memory. Therefore it is part of the program you download into the chip, and cannot be edited as the program runs. You can *only* change it by reprogramming the entire chip using the PICAXE software.

Therefore see the table (10.5) in the Microchip datasheet already mentioned (10k). If you are using it by reprogramming the chip once every 4 years it wll outlast any of our lifetimes quite comfortably!
 

pmolsen

Senior Member
What I really meant was that it is a separate area of memory. In other words, if I read the manuals correctly, on the 18M2+ it provided an ADDITIONAL 512 bytes of storage that does not eat into the amount available for program storage.
 
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