Decoupling on 40X2

[Circuit]

I note in Microchip's presentation on power considerations for PICs ( http://ww1.microchip.com/downloads/en/DeviceDoc/power.pdf ) that they advise that both Vdd power lines should be supplied externally - I know that this subject has been discussed before on this forum, but I also note that they advise "Ideally, a ceramic bypass capacitor of about 0.1uF is placed as close as practically possible to each power pin on the microcontroller". I have not seen mention of this before and therefore I thought to highlight it on this forum. I presume that this means that we should, ideally, be placing two decoupling capacitors on the power lines of the 40X2s; one on each power pin.

I also have a recollection of reading somewhere that, again "ideally", the reset pin should be held high with the 4K7 resistor but this should also be decoupled with a 1nF capacitor. Could one of the grown-ups confirm that this is the best way of designing things?

 

[JimPerry]

Pretty sure that it means one AS CLOSE AS POSSIBLE TO THE POWER PINS - OTHERWISE IT'S 200Nf (excuse CAPS LOCK)

 

[Circuit]

Pretty sure that it means one AS CLOSE AS POSSIBLE TO THE POWER PINS - OTHERWISE IT'S 200Nf (excuse CAPS LOCK)

Although the capacitance becomes 200nF, I don't think that this is the same as placing a 200nF capacitor on the circuit. With respect to 100nF on each power pin, remember that every operational i.c. on the circuit board should have 100nF (or whatever is appropriate) on its power pins; all these are in parallel but they are not eliminated by placing a single summatively large capacitor as a replacement. For decoupling and filtering purposes it is often common practice to place more than one capacitor on the power pins; for example from one commercial circuit board I have noted a parallel chain of 4.7uF; 47nF; 100nF and 47pF to decouple the power pins across a range of frequencies. I guess that the question is "close, how close?". I remain of the opinion that Microchip imply that best practice is putting 100nF ceramic on each power pin, though I do accept that as we have all been putting one 100nF on the joint supply to the two pins the bottom line is that it works without noticeable problems.

I am minded, though, to put a surface-mount ceramic 100nF between the Vdd and Vss pins on each side of the 40X2 chips in future.

- And should I be putting 100nF to ground from the Reset pin? Anybody?

 

[inglewoodpete]

I guess that the question is "close, how close?".

As close as practicable. When using stripboard with some microcontrollers (Eg the PICAXE M and M2 series), it is not easy to mount the capacitor really close. I have not had a problem mounting the cap 1 cm away from the chip. Remember, while you're trying to keep external noise out of the chip, half of the noise can be generated within the chip (especially if you are doing something like PWMing an LED).

I am minded, though, to put a surface-mount ceramic 100nF between the Vdd and Vss pins on each side of the 40X2 chips in future.

This is a simple solution that I have used several times in the past.

- And should I be putting 100nF to ground from the Reset pin? Anybody?

That's a different kettle of fish. There are two reasons for a capacitor on the reset pin: 1) noise reduction when using long reset leads and 2) holding the reset line low during power up (usually a slightly larger capacitor though). PIC chips (and PICAXEs) do not seem to need the reset pin held low during boot up.