Connecting two outputs to one input

Hi. I want to connect an output from two 08M2 chips to a single input of an 18M2 so that either/or of the outputs will trigger the 18M2 input. I understand that I need to place a 1k resistor in series from each of the outputs but that will mean the two outputs are then connected together with a 2k resistance. I will also add a pull up (or pull down) resistor to the input of 18M2. So in effect I am just trying to achieve an OR gate. Will this work OK with all combinations of High and Low outputs from the 08M2s?

As an afterthought I have in my box a bunch of 74xx chips and could use an OR or NOR gate from one of those but don't really want the bother of adding additional hardware and wiring if I can help it. Many thanks in advance. Terry
 

AllyCat

Senior Member
Hi,

Using two resistors of the same value (with or without a pull-up) very probably will NOT work, because a "half-Vdd" voltage is nearly always read as a "1". One solution, which needs no external components at all, is to use a "wired OR" connection, just link the three pins together but don't write Low / High to the output pins but Low / Input (or Low / Reverse). Then enable the "Weak PullUp" resistor on the INPUT pin of the 18M2 (or actually any or all of the pins).

But that is a little "risky" if you accidentally set an output pin High (or if you're using a hardware output like PWM), so the safe solution is to use two diodes (cathodes to output pins) and a pullup resistor (external or WPU) as described by Aries and Buzby. No need for series resistors, so you could just replace the (two output) resistors with diodes in the configuration you described in #1.

EDIT: Sorry, I've described an AND .gate function :( Two Resitors alone might work as an OR, or you may need to add a Pull DOWN resistor and/or with Diode Anodes connected from the Outputs. Another possibility it to use "Negative Logic" : Do exactly as I described above, but the "Normal" output levels are High (1) and pulling either Low gives the "OR" function (0) . ;)

Cheers, Alan.
 
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Many thanks for your input guys, much appreciated. So after reading about diode logic (I should know this stuff!) as suggested by Buzby I have sketched a proposed solution, attached. The input to 18M2 is held low via R1 and R2 until either of the 08M2 outputs goes high. R2 acts as current limiter here. Comments please?IMG_20200717_122403.jpg
 

jscottb

Active member
Many thanks for your input guys, much appreciated. So after reading about diode logic (I should know this stuff!) as suggested by Buzby I have sketched a proposed solution, attached. The input to 18M2 is held low via R1 and R2 until either of the 08M2 outputs goes high. R2 acts as current limiter here. Comments please?View attachment 24024
Out of all the DDL I had to do in school, this is the one DDL gate I use A LOT. So much smaller than wrapping nand gates with a 7400 or a real OR gate chip. I don't even think I have any 7400 series OR's and only a few in the 4000's
 
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