ADF4351 PLL success load with a PICAXE20x2

[vk3gjm]

Hi,

I am trying to make a 20x2 load a single frequency for a local oscillator.

It appears to load, see logic capture below and the default freq shifts from 4.5GHz to 3.693GHz, but that falls short of the mark.

Question without notice, has anyone tried a 20x2 on a ADF534x?



'VK3GJM, 2021
'Sketch to load single Freq to ADF4351, cheap Chinese black PCB
#picaxe 20x2
#No_Table
#No_Data
hspisetup spimode00,spimedium 'sets High Speed SPI port
symbol LE = C.0 'pin 10 C.0 Latch Enable
symbol sck = B.7 'pin 11 B.7 hspi sck
symbol sdo = C.1 'pin 9 C.1 hspi sdo
'pin 13 B.5 hspi sdi, not used and tied to ground via 10K
InitADF: 'sets ADF4351 for 39410.7MHz using a 25MHz reference Frequency with a PFD frequency of 25MHz
high LE
pause 1000
low LE
'Write R0
hspiout (0x4e,0x03,0x58)
'Write R1
hspiout (0x80,0x08,0x7d,0x01)
'Write R2
hspiout (0x4e,0x42)
'Write R3
hspiout (0x4b,0x3)
'Write R4
hspiout (0x8c,0x80,0x3c)
'Write R5
hspiout (0x58,0x00,0x05)
high LE

Thank you

 

[AllyCat]

Hi,

I've never used the ADF4351 (nor even SPI on a 20X2) but its Data Sheet appears to say:

"Data is clocked into the 32-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of six latches on the rising edge of LE. The destination latch is determined by the state of the three control bits (C3, C2, and C1) in the shift register. As shown in Figure 2, the control bits are the three LSBs : DB2, DB1, and DB0."

Are you sure that the HSPISETUP Mode 0 is MSB first, because the SPIOUT Mode 0 appears to be LSB first?

I couldn't see if the "Reserved" values should be set to "0", but IMHO it would at least be "safer" (until it is working correctly) to always send 4-byte packets. However, the Program and Logic Analyser suggests that you are transmitting variable-length packets. But I can't see any more from the Logic Analyser because the clock/data phase information is far too compressed, and even its "decoded" data seems to be incompletely displayed and inconsistent with the sequence of bytes in the program?

There also appears to be the requirement on Page 20 that:

"registers should be started in the following sequence:
1.Register 5
2.Register 4
3.Register 3
4.Register 2
5.Register 1
6.Register 0".

Cheers, Alan.

 

[vk3gjm]

Hi Alan,

I will experiment some more this evening. I found a doc form an other site using Arduino, the author also showed R5 to R1 and LE transition high to low then low to high in between each R dump.

Regards

Gerald