A "Vdd Sweeper" and Enhanced PICaxe Programming Interface


Senior Member

For any project which uses an unstabilsed supply (e.g. batteries), it's worthwhile to check that it functions correctly over the whole range of likely supply voltages. For Alkaline (and similar) cells this can be quite a large range, ideally from 1.55 volts per cell down to at least 1.1 volts (which also allows rechargeable NiMH cells to be used). However, my primary purpose was for several recent projects which have required characterisation of the PICaxe operation over its full supply voltage range, i.e. from 5.5 volts down to less than 2 volts. Therefore I breadboarded a very simmple "Vdd sweeper" to slowly reduce the supply rail voltage from the maximum until the PICaxe "stopped working".

The circuit was very simple, just a 6 volt battery feeding an NPN emitter follower (emitter to the PICaxe Vdd) with its base connected to both a large electrolytic capacitor (negative terminal grounded) and a "flylead". In operatation, the flylead was briefly touched onto the battery positive terminal (to charge the capacitor), then the capacitor allowed to slowly discharge over several minutes (the only drain is the small base current of a few uA). The voltage doesn't ramp down entirey linearly, but the PICaxe can report its actual Vdd via SERTXD (using CALIBADC10). Then characteristic graphs plotted against voltage (rather than time) by using the X-Y option in Excel (or similar spreadsheet program). If necessary, a "Hard Reset" (for reprogramming) could be initiated by touching the flylead onto the battery negative terminal.

This test rig performed remarkably well, but I was slightly concerned that the solderless breadboard "lash-up" carrying a large electrolytic and a flylead might accidently "release the magic smoke" from the PICaxe. Also, I noticed that all my PICaxes stopped working at exactly the same supply voltage, and then realised that it was the serial communications (SERTXD) which were dropping out (CH340 USB chip) and the PICaxe was still running happily.

Therefore, I decided to build a combined interface board for Vdd-Sweeping with a buffer-amplifier for the SerOut signal. It could be built as a motherboard (i.e. with a socket for the PICaxe chip(s)), but I chose to construct it as a "daughterboard" with four pins at one end to "piggyback" just the four end pins (two each side) of any 08, 14 or 20 pin M2. As is common with my designs, there are numerous "optional" features and/or components which perform more than one function, so it might be built as just an enhanced programming interface, or as a "Vdd sweeper", or with various combinations from both. ;)

The schematic diagram is shown below, with the first point of note that the toggle switch is a "Centre Off" type, which is important because the centre position is the basic "run" (sweep) position. However, if such a switch is not available then it can be replaced by two switches (an on/off and a push-button), or some of the functions may be omitted. Later in this post is a second schematic diagram that shows ALL the alternative component arrangements which might be "mix and matched" with the first diagram as required.


The 100 ohm resistor limits the current charging the electrolytic, the resistance might seem low but is (theoretically) required to achieve the dv/dt (risetime) specified in the PIC data sheet. The electrolytic capacitor might be any value between 100 uF and 10,000 uF depending on the required slew rate, the Vdd load current and the transistor gain. Generally 1,000 uF should be sufficeint, but I needed 4700 uF to achieve less than 1 mV/second for some crittical measurements.

The potentiometer and the additional discharge circuit are "optional": The pot is set to its lowest postion to force a Hard Reset (when closing the toggle switch) or it allows any (constant) supply voltage to be set for the PICaxe. The optional disharge components (diode + 120k) increase the speed of ramping down, either only down to a threshold voltage (set by the pot) or all the way to the PICaxe's dropout. The slowest ramp is obtained when the pot is set to the top of its track.

The primary purpose of the (optional) LEDs is to verify serial communications, one for the "break" signal (or program downloading) and the other for data transmission from the PICaxe. As the current in these LEDs is quite small, they generally need to be an Ultrabright type. Note that the "SerOut" LED does NOT specifically indicate a "High" on the pin, it indicates that the pin is "Not Pulled Low". Thus this LED lights (also) if the PICaxe is not fitted or when reset, etc..

The LED in the SerIn path has a secondary function: it blocks the negative voltage coming from a "real" RS232 port, which can inject a current into the PICaxe that upsets ADC measurements. However, the reverse breakdown voltage of a LED is rather low, so if the negative voltage blocking is a serious requirement, then a conventional diode is preferable (as shown in the alternative schematic diagram below). If not fitted, then this LED/diode must be replaced by a link (all other optional components should just leave an open circuit).

Similarly, the secondary function of the SerOut LED is to clamp the base of the transistor near to ground, so that the base-emitter junction can become reverse-biassed and remove any loading on the pin. This allows the SerOut pin to be used in its DAC output mode above about 1 volt, but again if this is a "serious" requirement then the alternative of two normal diodes might be preferable.


A sample Veroboard layout and typical software will be included in the next post.

Cheers, Alan.


Senior Member
Contruction and sample Software


Usually, I build my prototypes on "Veroboard" (stripboard) and find that "Pebble" is extremely useful both for organising the initial components' layout and for documenting the final design. However, Pebble does have a rather limited selection of component footprints, which constrains the exact layout particularly as here, where I use the tracks at right-angles to the normal orientation (e.g. if a PICaxe IC were on a motherboard).

The layout shown below is intended only as an example arrangement for a board of 8 x 30 holes (20 x 75 mm). The version I actually constructed is 6 x 25 holes (0.6 x 2.5 inches) with a "thumbwheel" pot at the end of the board, for easier access between finger and thumb. Also, a pot of the style shown in the Pebble footprint should be rotated by 180 degrees to that shown, so that clockwise rotation causes an increase in voltage.

For compactness, I used a three pin header for the programming socket (earth in the middle) but it should be possible to fit the standard 3.5 mm jack socket if preferred. It probably would need to be rotated at 90 degrees to the Pebble footprint.

A few more comments on the layout: Two timing capacitors are shown because the "Large Capacitor" Pebble footprint has its leads spaced too far apart, but normally a single capacitor should be sufficient. The transistors are both "emitter-down" (towards the PICaxe) but one has its base lead bent to the right, the other to the left.

The two LEDs are shown bridging a "cut track" hole. But I used adjacent holes, either with the track cut between holes (two cuts with a craft knife and flip the intervening copper off with the tip of a hot soldering iron) or take one of the leads through a "cut" spotface hole and bend the wire underneath to solder onto the appropriate track.


I have posted several graphs from this hardware on the forum, but here is sample software which compares two types of "improved" CALIBADC (Vdd measurement) algorithm (described in more detail in posts in the "Code Snippets" section). Either (or both) of these subroutines might be used as a "timebase" (X-axis) for other measurements, where a linear voltage scale is required:

; Comparison of Higher Resolution CALIBADC subroutines -  AllyCat November 2015
#picaxe 08M2		; Or any M2 picaxe 
symbol CALIBCONST = 512	; Adjust this slightly to correct for any minor errors in the FVR voltage
symbol CALVDD = 52429	; Nominally 1024*1.024*1000/20  (DAC steps * Ref V / Resolution in mV)

	call calibadc15			; "High resolution" Vdd measurement subroutine (Vdd > 2.2v)
	sertxd(cr,lf,"Vdd= ",#w1," mV ")
	call calibadc11			; "Medium resolution" full-range Vdd measurement subroutine
  	sertxd(#w1,"0 mV")	; Report the result, adding a zero to indicate mV
	pause 2000

calibadc11:			; "Medium resolution" full-range Vdd measurement subroutine
	calibadc10 w1			; Measure FVR (nominal 1.024 v) relative to Vdd (1024 steps)
	w2 = w1 / 2 + CALVDD	; Effectively round up CALVDD by half a (result) bit
	w2 = w2 / w1			; Take the reciprocal to calculate (half) Vdd (tens of mV)
	calibadc10 w1			; Read the value again because noise may be present :)
	w1 = CALVDD / w1 + w2	; Calculate Vdd/2 again and add in the first value
calibadc15:					; Measure supply rail using "15 bits resolution"	
	fvrsetup FVR2048		; Nominal 2 volt reference voltage
	dacsetup $88			; Reference chain to FVR
	adcconfig 0				; ADC ref to Vdd
	calibadc10 w3			; Initialise accumulator with CALIBADC10
	for b1 = 1 to 31 		; 15 pairs of daclevels each totalling 32 + middle value (=CALIBADC10) 
		daclevel b1			; Set the DAC attenuation value (32 steps to full-scale)
		readdac10 w2		; Read voltage on the "wiper"
		w3 = w3 + w2		; Accumulate the sum	
	next b1	
	w1 = 0					; Clear low byte of numerator
	w2 = CALIBCONST		; High byte of numerator, then fall into division routine    
div31:            		; Divide numerator (w2:w1) by divisor (w3) no error check
   for b1 =  0 to 15  	; Repeat for each bit positions
   w2 = w2 + w2 + bit31	; Shift High word of numerator left (top bit is lost), adding carry from w1
   w1 = w1 + w1      	; Shift Low word of numerator left
   if w2 >= w3 then    	; Skip if can't subtract
   	w2 = w2 - w3		; Subtract divisor, then.. 
   	w1 = w1 + 1    	; Add the flag into the result (in low word)
   next b1
   return					; Result is in w1, remainder in w2, divisor in w3 is unchanged
Cheers, Alan.