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    Inaccuracy with background serial receive on 20X2

    And that could finally make sense as to why the resistor makes a difference... I'm going to swap out the last inverter for a 2N2222 driver and see what effect that has. The serial gate/opto chain works fine and returns a good, clean, square round trip signal all the way down the line... but...
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    Inaccuracy with background serial receive on 20X2

    Some clarifications on points raised above. First it is not a battery operated project, so the power issue wasn't considered. Also, it's only a partial circuit diagram. All device inputs everywhere are terminated correctly. There are no unused gates as the extras are used for other...
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    Inaccuracy with background serial receive on 20X2

    Opto pull-up is 10K. A simplified version of the circuit schematic is attached (there's also a bunch more I/O - sensor inputs, output LEDs, and so forth... but they're not even exercised in my testing so far). The intent is that every 20X2 in the chain receives what the PC sends (as long...
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    Inaccuracy with background serial receive on 20X2

    Yes, there is decoupling on each opto, per the datasheet.
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    Inaccuracy with background serial receive on 20X2

    It is "series wired" not "parallel wired"... but It's not a daisy-chain where each node retransmits... the goal was to not have every board having to retransmit everything. Each board in effect sees what the PC transmitted... just buffered further down the line (more gates and optos). The...
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    Inaccuracy with background serial receive on 20X2

    Power and ground check out fine. I've only tried with one 20X2 target (I've only wired up one) but I have wired up a string of the gates and optos to simulate the environment the 20X2 would be in with multiple real boards... and to see how the signal looked at the end of the chain (and it...
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    Inaccuracy with background serial receive on 20X2

    I have checked it with a scope. Clean, square, symmetrical waveform. And the PC that is injecting the data at the start of the train of gates can correctly read the data that comes out the other end of the chain. Think a single long serial chain like this: PCTX - opto - 3 gates - opto - 1...
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    Inaccuracy with background serial receive on 20X2

    I initially thought it was random garbage... but then discovered the pattern noted above that the mis-reads are always the same data. When 41 hex ('A') is mis-received it is ALWAYS mis-received as hex D0. When 43 hex is mis-received it is ALWAYS mis-received as hex A1. The super-fast...
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    Inaccuracy with background serial receive on 20X2

    The Hardware receive on the 20X2 is being driven by the output of a 74F00 NAND gate. The original source of the serial data is either a PC or another 20X2 (both situations can exist and both have been tested with the same result) through a fast optoisolator (TLP2662F) and a few NAND gates...
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    Inaccuracy with background serial receive on 20X2

    Some further digging on the "inaccuracies" at 300 baud... 4D (01001110) received as E9 (11101001) or D3 (11010011). 41 (01000001) received as D0 (11100000). 43 (01000011) received as A1 (10100001). So looking at the mis-read bit patterns, it looks like a read bit time synchronization issue...
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    Inaccuracy with background serial receive on 20X2

    The code is really simple: hsersetup B300_8,1 gosub ledon pause 100 gosub ledoff pause 1000 MAIN: do pause 50 do while ptr <> hSerPtr b0 = @ptrInc if b0 = 65 then gosub ledon if b0 = 66 then gosub ledoff loop loop ; ledon...
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    Inaccuracy with background serial receive on 20X2

    Something rather odd with background serial receive on a 20X2. I'm driving the HSERIN pin (aka B.6) from the output of a 74F00 logic gate, that itself receives the serial signal from an opto-isolator. If I connect the gate output directly to HSERIN, then I get wildly inaccurate serial reads -...
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    Is Hserin really this slow?

    Doing the following seems to handle overruns: ; if nothing received, check for FIFO overrun peeksfr RCSTA,b0 ; look at OERR bit if bit1 <> 1 then fifook peeksfr RCREG,b6 ; read the FIFO twice, then... peeksfr RCREG,b6 hsersetup B300_4, 0 ; redo hsersetup to clear the error fifook:
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    Is Hserin really this slow?

    Although now of course it is possible to overrun and lock up the serial receive if I send too many characters while the code is busy doing something else. I guess what I need is a good way to do a reset when I know I've reached the end of a protocol sequence and am not expecting any more...
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    Is Hserin really this slow?

    Update: changed my code from an HSERIN to this: peeksfr PIR1,b0 if bit5 <> 1 then noseree peeksfr RCREG,b6 gosub gotser noseree: and it seems to receive flawlessly with no inter-character time required.
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    Is Hserin really this slow?

    Just found this thread because I've been having similar problems with hardware serial receive on a 14M2. What I've discovered from looking at the bit patters of the erroneously-received characters is that they are starting late. Looks like the hardware is missing the start bit, and...
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    Reading hardware serial input pin

    On an M2 part... is it possible to read the input state of the HSERIN pin independently of the background serial receive also watching it? Especially since the background serial receive is a bit different on the M2s. The documentation doesn't describe any interaction between hardware serial...
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    ADC channel numbers

    I'm using command line compiler on Linux so no PE or wizards at all. And yes I get which pins have capability... it was more a question of converting pin numbers to ADC channel numbers as the readadc example used the channel number. But if the compiler will auto convert then that isn't an issue.
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    ADC channel numbers

    Ah, I see. There's some confusion as the code example for readadc references the channel number (an integer) not the port number like C.0 : main: readadc 0,b1
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    ADC channel numbers

    I still don't see where that adcsetup reference actually indicates the ADC channel to pin mapping for an M2 part.
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